1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method thereof and more particularly, to a semiconductor device having a conductor plug formed in a contact hole of an interlayer dielectric layer, which is applicable to a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) or semiconductor memory device using MOSFETs, and a fabrication method of the device.
2. Description of the Prior Art
In recent years, the integration and miniaturization level of memory cells of semiconductor memory devices has been increasingly progressing. In response to this trend, there has been the strong need to improve the pattern-to-pattern or mask-to-mask overlay accuracy for patterned semiconductor, dielectric, and metal layers constituting the semiconductor memory devices. At the same time as this, permissible pattern-to-pattern or mask-to-mask alignment margins have been increasingly reduced. As a result, to cope with the above trend, conventionally, reconsideration of the structure and fabrication processes of the electronic elements or components constituting the semiconductor memory devices has been being carried out.
For example, with a MOS semiconductor memory device using MOSFETs, source/drain regions formed in a semiconductor substrate and wiring layers formed over the source/drain regions through an interlayer dielectric layer are electrically connected with each other by conductive members termed "contact plugs" or "conductor plugs" formed to vertically penetrate through the interlayer dielectric layer. The contact or conductor plugs are located in contact holes that are formed to penetrate vertically the interlayer dielectric layer and to interconnect the underlying source/drain regions with the overlying wiring layers.
The reduction of the pattern-to-pattern or mask-to-mask alignment margin will increase the danger that electrical short-circuit takes place between the wiring layers and the source/drain regions due to the conductor plugs. In other words, if the placement or overlay error of the masks or patterns in the fabrication processes is greater than a specific limit, electrical short-circuit between the wiring layers and the source/drain regions tends to frequently occur. This situation will degrade drastically the fabrication yield and reliability of the semiconductor memory devices.
To present the above-described problem relating short-circuit from occurring, conventionally, various improvements have been researched and developed.
FIGS. 1A to 1D show a conventional fabrication method of a semiconductor device, which was developed to solve the above problem and disclosed in the Japanese Non-Examined Patent Publication No. 2-285658 published in 1990.
Actually, a lot of source/drain regions are formed in a single-crystal silicon (Si) substrate and therefore, a lot of gate electrodes and a lot of contact holes are formed over the substrate. However, for the sake of simplification of description, one of the source/drain regions, one of the contact holes, one of the contact plugs, and two ones of the gate electrodes are only shown in FIGS. 1A to 1D and explained below.
First, as shown in FIG. 1A, a single-crystal Si substrate 101 having a source/drain region 101a in its surface area is prepared. Then, a silicon dioxide (SiO.sub.2) layer 102 serving as an interlayer dielectric layer is formed on the surface of the substrate 101. A conductive layer (not shown) is formed on the SiO.sub.2 layer 102 and patterned, thereby forming two gate electrodes 105 of MOSFETs on the SiO.sub.2 layer 102 so as to locate the source/drain region 101a between the gate electrodes 105. The gate electrodes 105 run along the surface of the substrate 101, which extend vertically with respect to the paper. Parts of the SiO.sub.2 layer 102 just below the gate electrodes 105 serve as gate insulators of the MOSFETs. The state at this stage is shown in FIG. 1A.
Subsequently, as shown in FIG. 1B, a Boron-doped PhosphorSilicate Glass (BPSG) layer 108 is deposited on the SiO.sub.2 layer 102 as an interlayer dielectric layer covering the gate electrodes 105. Then, using a patterned photoresist film (not shown) by a photolithography technique, the BPSG layer 108 and the underlying SiO.sub.2 layer 102 are selectively etched to form a contact hole 109 uncovering the surface of the substrate 101 between the adjoining gate electrodes 105. The contact hole 109 has, for example, a rectangular or circular plan shape. The bottom of the contact hole 109 reaches the underlying source/drain region 101a.
In FIG. 1B, the contact hole 109 deviates laterally from its desired or correct position to the left-hand side. At the desired or correct position, the contact hole 109 is apart from the adjoining two gate electrodes 105 and located in the middle of the source/drain region 101a.
A dielectric layer (not shown) made of SiO.sub.2 or silicon nitride (Si.sub.3 N.sub.4) is deposited on the BPSG layer 108 and is etched back, thereby selectively leaving the dielectric layer in the contact hole 109. Thus, a pair of sidewall spacers 103 are formed at opposing inner sides of the contact hole 109, as shown in FIG. 1C. The pair of sidewall spacers 103 serve to prevent a contact plug to be filled in the hole 109 in later process steps from being contacted with the gate electrodes 105.
Next, a polysilicon layer (not shown) is deposited on the BPSG layer 108. The thickness of the polysilicon layer is determined so that the polysilicon layer fills the contact hole 109. The polysilicon layer is then etched back until the surface of the underlying BPSG layer 108 is exposed, thereby selectively leaving the polysilicon layer thus deposited only in the contact hole 109. Thus, a contact plug 110 is formed in the contact hole 109 by the remaining polysilicon layer, as shown in FIG. 1D. The bottom of the plug 110 is contacted with the source/drain region 101a of the substrate 101. The opposite sides of the plug 110 are apart from the corresponding gate electrodes 105 by the sidewall spacers 103.
Thereafter, as shown in FIG. 1D, a conductive layer (not shown) is formed on the BPSG layer 108 and is patterned to have a specific plan shape, resulting in a wiring layer 111 on the BPSG layer 108. The bottom surface of the wiring layer 111 is contacted with the top of the contact plug 110.
Through the above-described process steps, the wiring layer 111 is electrically connected to the source/drain region 101a of the substrate 101 through the polysilicon plug 110. Typically, the wiring layer 111 serves as bit lines of a MOS semiconductor memory device.
With the conventional fabrication method of a semiconductor device shown in FIGS. 1A to 1D, the above-described problem of the electrical short-circuit can be solved. However, after the contact hole 109 is formed to penetrate the BPSG layer 108 and the SiO.sub.2 layer 102, the sidewall spacers 103 are formed within the contact hole 109. Thus, the effective or available size of the contact hole 109 is decreased due to existence of the sidewall spacers 103, raising another problem that the contact resistance at the contact plug 110 is increased.
FIGS. 2A to 2D show another conventional fabrication method of a semiconductor device, which was developed to solve the above problem of the electrical short-circuit.
First, as shown in FIG. 2A, after a single-crystal Si substrate 201 having a source/drain region 201a in its surface area is prepared, a SiO.sub.2 layer 202 serving as an interlayer dielectric layer is formed on the surface of the substrate 201. A conductive layer (not shown) is then deposited on the SiO.sub.2 layer 202 and a Si.sub.3 N.sub.4 layer (not shown) is deposited on the conductive layer thus deposited. The Si.sub.3 N.sub.4 layer and the conductive layer are patterned to have a same specific shape, thereby forming gate electrodes 205 made of the conductive layer and dielectric caps 204 made of the Si.sub.3 N.sub.4 layer on the SiO.sub.2 layer 202. The dielectric caps 204 are located on the gate electrodes 205. Parts of the SiO.sub.2 layer 202 just below the gate electrodes 205 serve as gate insulators.
Subsequently, as shown in FIG. 2B, a Si.sub.3 N.sub.4 layer (not shown) is formed on the SiO.sub.2 layer 202 to cover the gate electrodes 205 and the dielectric caps 204. The Si.sub.3 N.sub.4 layer is then etched back to be selectively left at both sides of the gate electrodes 205 and the caps 204. Thus, two pairs of sidewall spacers 207 are formed on the SiO.sub.2 layer 202. Each of the pair of sidewall spacers are located at two opposite sides of a corresponding one of the gate electrodes 205 and a corresponding one of the caps 204, as shown in FIG. 2B.
At this stage, the top face of each gate electrode 205 is covered with the Si.sub.3 N.sub.4 cap 204 and the two side faces thereof are covered with the pair of Si.sub.3 N.sub.4 sidewall spacers 207, as shown in FIG. 2B.
Following this, as shown in FIG. 2C, a BPSG layer 208 is deposited on the SiO.sub.2 layer 202 as an interlayer dielectric layer covering the gate electrodes 205 and the dielectric caps 204. Then, using a patterned photoresist film (not shown) by a photolithography technique, the BPSG layer 208 and the underlying SiO.sub.2 layer 202 are selectively etched to form a contact hole 209 uncovering the surface of the substrate 201 between the two adjoining gate electrodes 205. The contact hole 209 has, for example, a rectangular or circular plan shape. The bottom of the contact hole 209 reaches the underlying source/drain region 201a.
In FIG. 2C, like FIG. 1B, the contact hole 209 deviates laterally from its desired or correct position to the left-hand side. At the desired or correct position, the contact hole 209 is apart from the gate electrodes 205 and located in the middle of the source/drain region 201a.
To prevent or suppress undesired etching of the Si.sub.3 N.sub.3 caps 204 and the Si.sub.3 N.sub.4 sidewall spacers 207, the etching process for the BPSG layer 108 and the SiO.sub.2 layer 202 is carried out under the condition that the etch rate of BPSG and SiO.sub.2 is sufficiently higher than that of Si.sub.3 N.sub.4.
A polysilicon layer (not shown) is then deposited on the BPSG layer 208, in which the thickness of the polysilicon layer is determined to fill the whole contact hole 209. The polysilicon layer is etched back until the surface of the BPSG layer 208 is exposed, thereby selectively leaving the polysilicon layer only in the contact hole 209. Thus, a contact plug 210 made of polysilicon is formed in the contact hole 209, as shown in FIG. 2D. The bottom of the plug 210 is contacted with the source/drain region 201a of the substrate 201.
Thereafter, as shown in FIG. 2D, a conductive layer (not shown) is formed on the BPSG layer 208 and is patterned to have a specific plan shape, resulting in a wiring layer 211 on the BPSG layer 208. The bottom of the wiring layer 211 is contacted with the top of the contact plug 210.
Through the above-described process steps, the wiring layer 211 is electrically connected to the source/drain region 201a of the substrate 201 through the polysilicon plug 210. Typically, the wiring layer 211 serves as bit lines of a semiconductor memory device.
With the conventional method shown in FIGS. 2A to 2D, unlike the conventional method shown in FIGS. 1A to 1D, each gate electrode 205 is covered with the dielectric caps 204 and the sidewall spacers 207 and therefore, the gate electrodes 205 are difficult to be exposed during the etching process for the contact hole 209. This means that the above-described problem of the electrical short-circuit can be solved.
However, the whole top face of each gate electrode 205 is covered with the dielectric cap 204 and the whole side faces thereof are covered with the dielectric sidewall spacers 207, where the caps 204 and the sidewall spacers 207 are made of Si.sub.3 N.sub.4 having a high dielectric constant. As a result, there is another problem that a parasitic capacitance due to the gate electrodes 205 and the wiring layer 211 becomes high.
Other conventional methods of this sort are disclosed in the Japanese Non-Examined Patent Publication Nos. 9-162388 and 9-246486 both of which were published in 1997.
In the conventional method disclosed in the Japanese Non-Examined Patent Publication No. 9-162388, after a gate electrode and dielectric sidewall spacers located at each side of the gate electrode are formed, a first dielectric layer is formed to cover the gate electrode and the sidewall spacers. Next, a second dielectric layer is formed on the first dielectric layer. The second dielectric layer is selectively etched to be removed from the bottom of the gate electrode to half of the height of the gate electrode, thereby forming a cap-shaped structure of the gate electrode while the lower half of the first dielectric layer is exposed from the second dielectric layer.
Thus, with the conventional method disclosed in the Japanese Non-Examined Patent Publication No. 9-162388, when a contact hole reaching an underlying source/drain region is formed by etching in an interlayer dielectric layer to be formed to cover the gate electrode, the second dielectric layer serves as an etch stop. Therefore, the gate electrode is prevented from being exposed in the etching process of the contact hole, resulting in prevention of the electric short-circuit problem between the gate electrode and the source/drain region.
However, the gate electrode and the sidewall spacers are entirely covered with the first dielectric layer and the upper half parts of the gate electrode and the sidewall spacers are further covered with the second dielectric layer. Accordingly, like the conventional method shown in FIGS. 2A to 2D, there is a problem that a parasitic capacitance due to the gate electrode and its adjoining wiring layer or layers becomes high.
In the conventional method disclosed in the Japanese Non-Examined Patent Publication No. 9-246486, after a dielectric layer is formed on a conductive layer, the dielectric layer is patterned to form an upper dielectric layer (i.e., cap layer) covering the top of a gate electrode. Then, using the upper dielectric layer as a mask, the conductive layer is patterned to form the gate electrode. Both sides of the gate electrode are then etched to make the width of the gate electrode smaller than that of the upper dielectric layer. Thereafter, dielectric sidewall spacers are formed at each side of the gate electrode.
Thus, with the conventional method disclosed in the Japanese Non-Examined Patent Publication No. 9-246486, after decreasing the width of the gate electrode by etching to make the width of the gate electrode smaller than that of the upper dielectric layer, the dielectric sidewall spacers are formed at each side of the gate electrode. Therefore, even if the thickness of the sidewall spacers is decreased, the above-described electric short-circuit problem between the gate electrode and the source/drain region is prevented from occurring.
However, the upper face of the gate electrode is entirely covered with the upper dielectric layer and the side faces of the gate electrode are entirely covered with the sidewall spacers. Thus, like the conventional method shown in FIGS. 2A to 2D, there is another problem that a parasitic capacitance due to the gate electrode and its adjoining wiring layer or layers become high.